This invention relates generally to computer memory, and more specifically, to adaptive write leveling in limited lifetime memory devices.
Phase-change memories (PCMs) and flash memories are examples of non-volatile memories with limited endurance (also referred to as a “limited life”). Such memories have limited endurance in the sense that after undergoing a number of writing cycles (RESET cycles for PCM, program/erase cycles for flash memory), the memory cells wear out and may no longer be able to reliably store information.
A typical unit of access to a memory is a block that may include tens to hundreds of device cells each of which may be storing one bit of data (single-level cell) or a few bits of data (multi-level cell). Each cell within a block may have a different lifetime than other cells in the same block due to the statistical nature of device manufacturing processes. Thus, cells within a block may fail at different times, rendering the entire block unusable. To help alleviate this problem, error checking and correcting (ECC) techniques are utilized within each memory block. Additional cells are used in each block to be able to encode data in a variety of manners to recover from cell errors, therefore prolonging the block life.
Some memory addresses (referred to as hot-spots) will be busier than others. In general, hot-spot blocks will fail sooner than less busy blocks. Hot spots, if not avoided, can render the entire memory (e.g., one or more memory devices) unusable due to a single bad block. Wear-leveling methods prolong the life of these memories by uniformly distributing writes/erasures across the whole memory such that every block receives an approximately equal number of writes over the lifetime of the whole memory.